A couple of years ago I got the opportunity to work on an FPGA design as part of an embedded Linux system. It was my first time using FPGAs and I found them both interesting and challenging. I recently saw this tweet from @ameellio that sums it up.
When I’m teaching I often forget what it was like as a beginner, so while this is all still fresh in my mind I want to write up some of the more important things I’ve learnt regarding FPGAs and also more generally, learning a new skill. In no particular order:
Find a mentor
While working on the embedded Linux system, I wanted to pay someone to do a code review for me and got in contact with Eric, who’d made an SDR project using FPGAs that got published on hackaday. It’s been great to get professional feedback on my work, something I feel I miss out on being mostly self-employed on short prototyping projects with very small teams.
Find the community
One thing I think people in technology often take for granted is the amazing access to community support. There are lots of great resources out there and getting involved with a community can help not only with getting answers to problems but lead to unexpected discoveries. I’m often guilty of getting stuck on a specific issue and then searching desperately for the answers, when a bit more of an overview and more general understanding would have been a better use of time. The best resources I’ve found have been the zipcpu blog, Obijuan’s tutorial (Spanish but translates well), FPGAwars google group (also Spanish) and the mystorm FPGA development board forum.
Find the tools
As a vim/makefile kind of developer, the first time I used a 10GB FPGA IDE was a bit of a shock! It was so great when I found out about the IceStorm tools – small, fast, easily used with makefiles. The documentation for these tools is great, and Clifford is also somehow supporting users on Reddit and StackOverflow. I’ve even seen yosys doing synthesis on a Raspberry Pi!
Different people prefer different tools, and often trying a few out can help you discover the right ones for you.
Find out how other people do it
I read Eric’s SDR code, and a few other projects I found interesting on github. Dan’s great series on FPGA hell was also an amazing resource. The real lesson I learnt here is that with FPGAs it’s a really good idea to spend more time up front with pen and paper before diving into the HDL. And then having a familiar debugging interface is invaluable. I currently use a combination of logic analyser, test benches and a serial port driven step debugger I found on Dan’s zipcpu site. The idea is to clock your design from the serial port while reading interesting registers into a VCD file, later visualised using GTKWave (love the GTKWave logo by the way!).
Find a project
At the end of 2009 I published a virtual graffiti system using Processing, a Nintendo wiimote camera and a rear projection screen. The system was cool, the kids loved it, but I was never really satisfied with the responsiveness of the system. Video seemed like something FPGAs were meant to be good at so I thought I’d make an FPGA virtual graffiti system. About a year of Sunday afternoon’s working has got me to a system I’m happy with (20ms delay due to 50Hz screen refresh), and a much greater understanding of what FPGAs are, when they’re useful, and how to develop for them.
Having a project I could work towards helped keep me going even in the middle a 2 month period of zero progress due to a weird issue with memory address lines and PLLs (turned out to be a board error).
The virtual graffiti system is hosted on github, and includes the Verilog source, test benches, Makefile and documentation.
Make documentation and present the project
A great way to really understand something is to try to teach it. I took my virtual graffiti system to Bilbao maker faire and although the majority of people were satisfied with a super simple explanation there were about 20 people over the weekend where I got a chance to try to explain to an expert in another domain what FPGAs are and how to design for them.
In the process of making the documentation, I learnt that yosys can use Graphviz to create interactive drawings of its synthesis – which gives an incredible insight into how the HDL is translated into the digital logic that an FPGA can support.
I discovered a big waste of resources just by looking at the size of the resultant pictures. It wasn’t until I was trying to explain the pictures at the maker faire that I realised I needed to read the paper again!
I also discovered IceFloorPlan, an interactive tool to explore how your design ends up on the logic blocks of the FPGA.
In the process of trying to automate making my system overview diagram I found a pyverilog, a Python library that can parse Verilog. I used this to generate Graphviz files for each module that were then imported into Inkscape for layout.
I hope you found something useful about either FPGAs or learning, feel free to leave other resources in the comments.